Certain digital circuits, such as microprocessors, maintain register file sets for various purposes, such as general-purpose data registers. In a microcontroller, defined as an integrated circuit comprising a microprocessor and one or more peripherals, registers are maintained for numerous purposes such as to store interrupt levels assigned to several peripheral devices. The register set is an array of random access memory cells, with multiple rows and columns, in which each row corresponds to a register, and each column corresponds to a bit position in the registers.
A useful function a microcontroller may perform on a register file is a comparison of binary values stored in each register. A binary magnitude comparator performs this function by making a bit-by-bit comparison of the contents of two or more enabled registers in the register file. Results of the comparison are a highest or lowest binary value in the register file, and signals from each of the registers which indicate whether the register contained the highest or lowest binary value. For example, a register set may indicate an interrupt priority level for each of several peripherals. The result of the binary magnitude comparison is the highest interrupt level of all enabled peripherals, and a signal for each peripheral indicating whether the peripheral had the highest interrupt level.
A typical binary magnitude comparator checks for a maximum value in a register file by first comparing a most significant bit from each enabled register. The result of the comparison is sensed, and if any registers have a binary `1` in the most significant bit position, or column, the result is sensed as a `1` for that column. All registers having a `1` in the most significant column proceed to compare the next column after the next occurrence of a clock edge. If all registers have a binary `0` in the most significant column, all registers proceed to compare the next most significant column. The operation continues to next most significant columns until all bits are compared. Only those registers containing a highest value through a given column may continue the comparison to next most significant columns. When the operation is complete, a binary value representing the highest valued register or registers is provided, along with a signal for each register to indicate whether the highest binary value was found in the register. A binary magnitude comparator implemented in this fashion is inherently slow, however, because successive column comparisons must wait for succeeding clock pulses. Furthermore, different parts of the digital circuit may contain register sets of different register widths and include a different number of registers, requiring the binary magnitude comparator to be re-designed for each register set.